-- Pacote dos divisores de clock

library ieee;
use ieee.std_logic_1164.all;

package PCT_DIV_CLOCK is

component DIV_CLOCK1 is
	generic
	(
		MIN_COUNT : integer := 0;
		MAX_COUNT : integer := 99
	);

	port
	(
		CLK, CLR : in std_logic;
		Q : out std_logic
	);
end component;

component DIV_CLOCK2 is
	generic
	(
		MIN_COUNT : integer := 0;
		MAX_COUNT : integer := 12
		
	);

	port
	(
		CLK, CLR : in std_logic;
		Q : out std_logic
	);
end component;

end PCT_DIV_CLOCK;